The Turbo Decoder block decodes the input signal using a parallel concatenated decoding scheme. The iterative decoding scheme uses the a posteriori probability (APP) decoder as the constituent decoder, an interleaver, and a deinterleaver. The two constituent decoders use the same trellis structure and decoding algorithm. The Turbo Decoder block decodes the input signal using a parallel concatenated decoding scheme. The iterative decoding scheme uses the a posteriori probability (APP) decoder as the constituent decoder, an interleaver, and a deinterleaver. The two constituent decoders use the same trellis structure and decoding algorithm.
Simulink models and MATLAB functions associated with the manuscript 'Anticipation from Sensation: Using Anticipating Synchronisation to Stabilise a System with Inherent Sensory Delay'
Contains two Simulink models that implement a simulation of a robot arm, along with control laws basedon anticipating synchronisation (AS), which were used to generate the results shown in the manuscript 'Anticipationfrom Sensation: Using Anticipating Synchronisation to Stabilise a System with Inherent Sensory Delay'.
Both models share a series of constants, which are labelled within the Simulink view, and allow the alteration of the robot'sdynamics (link lengths and link masses), as well as the parameters of the control law (gains, coordinate transformation,strength of AS coupling).
The MATLAB functions AnticiStep and AnticiStepDisturbance plot the anticipation/lag of the arm's end effector motion withrespect to the target, as well as the tracking error at that time difference. The result is plotted as a function ofdelay (feedback delay only or feedback and target delay) and coupling strength.
Library
Simscape / Electrical / Specialized Power Systems / Control & Measurements / Additional Components
Description
The Discrete Shift Register block outputs a vector containingthe last N samples of the input signal. When the input contains morethan one signal, the block outputs the last N samples of each signalin the following order:
Out = [u1(k), u1(k−1), u1(k−2), u1(k−3),u2(k), u2(k−1), u2(k−2), u2(k−3)]
This example shows the block output for an input containingtwo signals, represented by u1 and u2, and a number of samples N =4, represented by the k to k−3 indices. The dimension of theoutput vector is 4 × 2 = 8.
Parameters
Specify the number of samples, or stages, of the register. Theminimum value is
1
. Default is 32
.Specify the initial value of the N-1 samples preceding time
0
.Enter a scalar value or a vector of the same size as the input signal.Default is 0
.Specify the time interval between the samples. Default is
50e-6
.Characteristics
Direct Feedthrough | Yes |
Sample Time | Discrete |
Dimensionalized | Yes |
Scalar Expansion | Yes, of the parameter Initial inputs |
Zero-Crossing Detection | No |
Examples
The
power_DiscreteShiftRegister
exampleshows various uses of the Discrete Shift Register block.